3-2 Key characteristics for protection against ESD events(2)

3-2(2) Low clamp voltage (V_C) and first peak voltage

Figure 3.10 shows the response waveforms of ESD protection diodes with high and low clamp voltages (V_C) when an ESD waveform stipulated in IEC 61000-4-2 was applied to them. These waveforms were taken at the input of a device under protection (DUP). The ESD protection diode with a lower V_C exhibits lower clamp voltage at 30 ns and 60 ns than the one with a higher V_C. The smaller the area under the curve of the ESD waveform, the less damage the DUP suffers. Therefore, ESD protection diodes with low V_C provide better protection against ESD pulses. In addition, some ESD protection diodes do not respond immediately after the ESD entry. Therefore, if the first peak of the ESD pulse is higher than the V_C of the ESD protection diode, it might be applied to the DUP, leading to its malfunction or destruction. ESD protection diodes are designed to provide faster response than other types of protection devices. In addition, Toshiba is working on the optimization of the chip process and the internal device structure in order to further reduce the first peak voltage and therefore provide more rugged protection against the peak ESD voltage during the initial period.